Shallow trench isolation (STI) techniques have been developed to improve the local oxidation of silicon (LOCOS) process which is widely used in the manufacture of microelectronic devices. In a shallow trench isolation method, a semiconductor substrate is etched to form a shallow trench and insulating materials are buried in the trench to form an isolation layer. When using a conventional LOCOS process, the isolation layer is formed by thermal oxidation. When using a conventional STI method, thermal oxidation is not used. Accordingly, the use of the STI method reduces problems caused by thermal oxidation. For example, the bird's beak phenomenon which occurs at the boundary between the isolation region and an active region in a conventional LOCOS method can be reduced.
FIG. 1 is a cross-sectional view illustrating problems which may be associated with conventional trench isolation methods. The microelectronic structure of FIG. 1 includes a semiconductor substrate 100, and an oxide filling 200 in a trench region of the substrate which is formed by etching the substrate 100. The reference characters A and B respectively represent surface profiles of the oxide filling before and after a wet etch.
If the pad oxide and mask layers which are used to selectively form the trench are over etched during a wet etch, the upper sidewall of the trench region may be exposed as indicated by reference character C. Accordingly, when the gate insulating layer and the gate electrode of a MOS transistor are formed on the exposed sidewall of the trench region (the sidewall of an active region), a gate electric field may have a greater intensity at the edge of the channel than at the center of the channel. A parasitic channel may thus be formed at the sidewall of the active region even though a voltage lower than the threshold voltage is applied to the gate electrode. This parasitic channel may result in a hump phenomenon wherein the transistor turns on twice. In addition, the threshold voltage of the transistor may be reduced as the width of the channel region decreases resulting in an inverse narrow width effect.
When a shallow trench isolation method is used to provide isolation for highly integrated microelectronic device, the electrical characteristics of a MOS transistor formed thereon may depend on a profile of the edge of the trench. Accordingly, as the etch rate of the oxide 200 in the trench varies, the profile of the trench and oxide varies. As the profile varies so do the electrical characteristics of a MOS transistor formed adjacent thereto. Accordingly, because the etch rate of the oxide 200 is dependent on the densification process used, the characteristics of the MOS transistor are dependent on the densification process used. The process conditions used to densify the oxide 200 should thus be optimized.
A trench isolation method for CMOS device fabrication is discussed in the reference by Asanga H. Perea et al., entitled "Trench Isolation For 0.45 .mu.cm Active Pitch And Below", IEDM Tech. Digest, p. 679-682, 1995. In this reference, an ozonated APCVD TEOS oxide is annealed at 1,000.degree. C. to stabilize the deposited oxide film. The upper sidewall of the trench region, however, may still be exposed. Accordingly, there continues to exist a need in the art for improved shallow trench isolation methods.